1. Field of the Invention
The present invention relates to a static RAM.
2. Description of the Related Art
Recently, the operating frequencies of systems which implement static RAMs (hereinafter, referred to as SRAMs) have been on the increase. Moreover, SRAMs with lower power consumption have been demanded in particular for the sake of reducing entire power consumption of portable equipment. Under the circumstances, SRAMs with faster access time and smaller consumption current during a standby period (standby current) have been required.
Japanese Unexamined Patent Application Publication No. Hei 11-16363 discloses an SRAM containing memory cells each composed of six transistors, having the structure that the substrates (p-well regions) of transfer transistors and load transistors are connected to word lines.
In the SRAM disclosed therein, the transfer transistors and the load transistors decrease in threshold value when the word lines are turned to high level to access the memory cells, and increase when the word lines are turned to low level to retain data in the memory cells. At the time of accessing the memory cells, the currents flowing through the transfer transistors and the load transistors increase to shorten the access time. During standby, the transfer transistors and the load transistors decrease in leak current, thereby reducing the standby current.
Moreover, Japanese Unexamined Patent Application Publication No. 2000-114399 discloses an SRAM containing memory cells each composed of six transistors, having the structure that the gates of transfer transistors and driver transistors are connected to their own substrates. In addition, as with typical SRAMs, load transistors and driver transistors form two CMOS inverters having inputs and outputs connected to each other.
In the SRAM disclosed therein, the transfer transistors decrease in threshold value when the word lines are turned to high level to access the memory cells, and increase when the word lines are turned to low level to retain data in the memory cells. The driver transistors decrease in threshold value when their gates are given a low level. Then, at the time of accessing the memory cells, the currents flowing through the transfer transistors increase to shorten the access time. During standby, a CMOS inverter having its load transistor turned on, out of the two CMOS inverters composed of the load transistors and driver transistors, decreases in leak current, thereby reducing the standby current.
In such semiconductor integrated circuits as an SRAM, the substrate areas of transistors (well regions) are typically shared among a number of transistors in order to reduce the layout size of these transistors. In other words, a single well region is formed for a number of transistors. On this account, according to the conventional art described above, drivers for driving word lines must drive the loads of not only the word lines but also the substrates of the transistors when the word lines are connected to the substrates. As a result, it takes longer time to access the memory cells even when the threshold values of the transistors are lowered.
Besides, the sources and drains of the nMOS transistors constituting the transfer transistors and the driver transistors are made up of n-type diffusion layers. Consequently, if the high level voltage of the word lines is higher than the forward bias of the pn junctions, currents can flow from the substrates (p-type well regions) to the sources or drains of the nMOS transistors when the high level voltage of the word lines is supplied to the p-type well regions. This might result in a malfunction (data crash or incorrect data read) at the time of accessing the memory cells.